1. Field of the Invention
The present invention relates to circuits for controlling SDRAM (Synchronous Dynamic Random Access Memory) memories.
2. Related Background Art
SDRAM is a relatively new device created to enable an asynchronous DRAM (Dynamic Random Access Memory) to operate at a higher speed.
Although similar to a method for controlling known asynchronous DRAM, the SDRAM control method is characterized in that it uses a CLK signal for synchronization, it accesses the SDRAM using a command, it has sequential data read and write capability (burst mode), and so forth.
FIG. 4 is a timing chart showing standard access to an SDRAM that supports a burst length (BL) of 2.
In the actual method for accessing SDRAM, an SDRAM controller outputs an RAS address at the same time as issuing an ACTV command. Next, the SDRAM controller outputs a CAS address at the same time as issuing a WRITEA or READA command (hereinafter, unless otherwise stated, the next command can be accepted 1CLK after the ACTV command).
When the issued command is WRITEA, the SDRAM controller simultaneously outputs write data onto data bus lines and performs a write operation. When the issued command is READA, read data is output from the SDRAM after an intrinsic delay time (CAS latency=CL), and the SDRAM controller obtains the read data.
When the above-described WRITEA/READA commands are used, the burst number is a constant specified by the burst length (BL). In order to execute an arbitrary burst number, BL is changed by issuing a mode-register-set (MRS) command, and a combination of BLs is used to achieve the desired burst number. However, the total throughput is disadvantageously reduced. There is a method that does not use the above-described WRITEA/READA commands, and, instead, the burst operation is interrupted by the SDRAM controller when a desired burst number is reached.
FIG. 5 is a block diagram showing an example of the configuration of a general DMA (Direct Memory Access) controller. In general, DMA request blocks have different configurations depending on the application. On the other hand, memory controllers have different circuitry depending on the type of memory. It is thus preferable that an arbitration unit and a memory controller be independent of each other in order to facilitate accommodation of various applications and memories.
In this case, DMA request blocks 1-1 . . . 1-N output to an arbiter circuit 3 signals including DMA request signals DREQ_1 . . . N, address signals ADDRESS_1 . . . N, DR-WX_1 . . . N indicating whether a read or write request is issued, BSTNUM_1 . . . N indicating the burst number, write data bus WRDATA_1 . . . N, etc.
In contrast, the arbiter circuit 3 outputs to the DMA request block 1-1, . . . 1-N negative logic DMA request acknowledgement signals REQACKX_1 . . . N, read data bus RDDATA_1 . . . N, and negative logic memory access signals DTACKX_1 . . . N.
In this description, WRDATA and RDDATA are connected to all of the DMA request blocks 1-1 . . . 1-N. In actual use, each DMA request block may only perform a read or a write. In such a case, the unused data bus need not be connected. In FIG. 5, a circuit for controlling refreshing the SDRAM is omitted.
At the same time, the arbiter circuit 3 outputs to an SDRAM controller 4 signals including an arbitrated DMA request signal REQ, arbitrated address signal ADRS, arbitrated read/write identifying signal R-WX, BSTNUM indicating the burst number, write data bus WRDATA, etc. In contrast, the SDRAM controller 4 outputs to the arbiter circuit 3 a read data bus RDDATA and negative logic memory access signal ORG_DTACKX. With the above-described arrangement, interfaces between the arbiter circuit 3 and the memory controller 4 are standardized to accommodate various applications and memories.
FIG. 6 is a timing chart showing the overall operation of the DMA controller for performing such a control operation. In this example, the burst length is set in advance to a maximum of 8 when an initial MRS command is issued.
In this example shown in the chart, the DMA request block 1-1 independently issues a burst read DMA request, and, during the DMA processing, the DMA request block 1-2 issues a burst write DMA request.
The detailed control flow will now be described.
At T0, the arbiter circuit 3 waits for a DMA request from each DMA request block in its arbitration operation enabled state.
At T1, the DMA request block 1-1 simultaneously outputs DMA control information and enables DREQ (where DREQ is a read for a burst of 2).
Having acknowledged the reception of DREQ during T2, the arbiter circuit 3 determines whether or not another DREQ is output. If another DREQ is output, the arbiter circuit 3 arbitrates between the DMA request blocks to select the DMA request block on the basis of a predetermined priority and latches DMA control information concerning the selected DMA request block.
At T3, DREQACKX is sent to the selected DMA request block (DMA request block 1-1).
At the same time, the latched DMA control information is output to the SDRAM controller 4, and REQ is enabled. The arbiter circuit 3 enters the DMA request acceptance, arbitration, and selection disabled state.
In response to REQ, at T4, the SDRAM controller 4 outputs a row address by issuing an ACTV command. At T5, the SDRAM controller 4 simultaneously issues a READ command and outputs a column address. In the case of READ, an SDRAM 5 outputs read data onto DQ after CL (in this example, CL=2), that is, subsequent to T7, and the SDRAM controller 4 obtains the read data. In this example, when no command is issued, the state is the NOP (No Operation) state. Alternatively, the SDRAM controller 4 may be in its standby mode in the DESL or PD state.
The obtained data is latched by the SDRAM controller 4 and then sent to each DMA request block 1. While the data is being accessed, ORG_DTACKX is enabled to enable each DMA request block 1 to read the data.
ORG_DTACKX is sent to the arbiter circuit 3, and the arbiter circuit 3 in turn outputs ORG_DTACKX to the selected DMA request block (DMA request block 1-1), that is, it enables only DTACKX_1 (low level).
When DTACKX_1 is enabled, the DMA request block 1-1 reads the data at the time indicated by DTACKX_1 from RDDATA_1.
In contrast, the SDRAM controller 4 requests data access a desired number of times (twice) and then terminates the burst operation at T7 by issuing a PRE command.
When data is read the desired number of times (twice), the SDRAM controller 4 disables ORG_DTACKX signal (high level) at T9.
When the arbiter circuit 3 detects the rising of ORG_DTACKX signal at T10, the arbiter circuit 3 cancels the DMA request acceptance, arbitration, and selection disabled state at T11.
As a result, at T12, DREQ2 from the DMA request block 1-2 is acknowledged. It is then determined whether or not another DREQ is output. If another DREQ is output, arbitration and selection is performed on the basis of the predetermined priority.
In this example, since only the request from the DMA request block 1-2 has been output, DMA control information from the DMA request block 1-2 is latched.
At T13, DREQACKX is sent to the selected DMA request block (DMA request block 1-2).
At the same time, the latched DMA control information is output to the SDRAM controller 4, and REQ is enabled. The arbiter circuit 3 again enters the DMA request acceptance, arbitration, and selection disabled state.
In response to REQ, at T14, the SDRAM controller 4 outputs a row address by issuing an ACTV command. At T15, the SDRAM controller 4 simultaneously issues a WRIT command and outputs a column address.
In the case of WRIT, the DMA request block 1-2 outputs data to WRDATA_2 bus at the same time as issuing the WRIT command.
The data is output via the SDRAM controller 4 to DQ and actually written in the memory. While the data is being written in the memory, ORG_DTACKX is enabled.
ORG_DTACKX is sent to the arbiter circuit 3, and the arbiter circuit 3 in turn outputs ORG_DTACKX to the selected DMA request block (DMA request block 1-2), that is, it only enables DTACKX_2.
In this example, a burst write of three writes is instructed. After data is written three times, at T18, a PRE command is issued to interrupt the burst write, and ORG_DTACKX is disabled.
When the arbiter circuit 3 detects the rising of ORG_DTACKX signal at T18, the arbiter circuit 3 cancels the DMA request acceptance, arbitration, and selection disabled state at T19.
According to the known control method, the maximum number of sequential accesses to SDRAM is limited by the SDRAM settings. In general SDRAMs, the maximum number is 256, 8, 4, or 2.
There is a special relationship between the burst length and address. In the case of gaining the burst access to the SDRAM, the address is updated by a counter in the SDRAM. Since incrementing the address does not generate a carry into the next higher order even when a preset burst length is exceeded, different addresses are accessed when sequential accesses are tried starting from an arbitrary address. For example, when the burst length is set to 8, accessing the lower-order addresses 0Ch to 14H in five bursts actually results in accessing 0Ch, 0Eh, 00, 02, and 04.
In electronic apparatuses such as printers, the maximum number of sequential DMA requests ranges from approximately 10 to 100. Since the capacity of the built-in memory is not high, a system for accessing a column address at a boundary is difficult to configure.
In order to solve these problems, Japanese Patent Laid-Open No. 2000-215155 describes a controller that performs single transfer to the boundary and then performs burst transfer. Such a controller disadvantageously has a complicated circuit.
The number of DMA request blocks is approximately ten. When one DMA request block continuously accesses the SDRAM for a long period of time, the other DMA request blocks cannot perform the processing. As a result, the printer has a reduced throughput.
In these electronic apparatuses, a clock frequency supplied to the SDRAM is much smaller than the maximum clock frequency that can be received by the SDRAM. Therefore, when one DMA request block sequentially accesses the SDRAM for a long period of time, the memory is not refreshed properly.
Accordingly, a need arises for these electronic apparatuses to implement a memory control system that can start sequential access exceeding eight bursts at an arbitrary address using a relatively simple configuration.